%0 Journal Article %1 journals/jssc/OgiwaraTIMTDTKS00 %A Ogiwara, Ryu %A Tanaka, Sumio %A Itoh, Yasuo %A Miyakawa, Tadashi %A Takeuchi, Yoshiaki %A Doumae, Sumiko Mano %A Takenaka, Hiroyuki %A Kunishima, Iwao %A Shuto, Susumu %A Hidaka, Osamu %A Ohtsuki, Sumito %A Tanaka, Shin'ichi %D 2000 %J IEEE J. Solid State Circuits %K dblp %N 4 %P 545-551 %T A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. %U http://dblp.uni-trier.de/db/journals/jssc/jssc35.html#OgiwaraTIMTDTKS00 %V 35

@article{journals/jssc/OgiwaraTIMTDTKS00, added-at = {2022-04-13T00:00:00.000+0200}, author = {Ogiwara, Ryu and Tanaka, Sumio and Itoh, Yasuo and Miyakawa, Tadashi and Takeuchi, Yoshiaki and Doumae, Sumiko Mano and Takenaka, Hiroyuki and Kunishima, Iwao and Shuto, Susumu and Hidaka, Osamu and Ohtsuki, Sumito and Tanaka, Shin'ichi}, biburl = {https://www.bibsonomy.org/bibtex/29fb012b1af686f8c752907183a24839f/dblp}, ee = {https://doi.org/10.1109/4.839914}, interhash = {290321ba1c011b3fe4335aec9af4c9c7}, intrahash = {9fb012b1af686f8c752907183a24839f}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 4, pages = {545-551}, timestamp = {2024-04-08T10:43:01.000+0200}, title = {A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc35.html#OgiwaraTIMTDTKS00}, volume = 35, year = 2000 }