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Disambiguation of "Kunishima, Iwao"

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A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 35 (4): 545-551 (2000)

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Other publications of authors with the same name

A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM., , , , , , , , , and 9 other author(s). ISSCC, page 262-263. IEEE, (2010)A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode., , , , , , , , , and 5 other author(s). ISSCC, page 459-466. IEEE, (2006)A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 35 (4): 545-551 (2000)A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode., , , , , , , , , and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1745-1752 (2010)A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes., , , , , , , , , and 23 other author(s). ISSCC, page 464-465. IEEE, (2009)A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 46 (9): 2171-2179 (2011)