%0 Conference Paper %1 conf/vlsic/OnukiUTIAOKYLWS16 %A Onuki, Tatsuya %A Uesugi, Wataru %A Tamura, Hikaru %A Isobe, Atsuo %A Ando, Yoshinori %A Okamoto, Satoru %A Kato, Kiyoshi %A Yew, Tri Rung %A Lin, Chen Bin %A Wu, J. Y. %A Shuai, Chi Chang %A Wu, Shao Hui %A Myers, James %A Doppler, Klaus %A Fujita, Masahiro %A Yamazaki, Shunpei %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#OnukiUTIAOKYLWS16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/OnukiUTIAOKYLWS16, added-at = {2017-04-07T00:00:00.000+0200}, author = {Onuki, Tatsuya and Uesugi, Wataru and Tamura, Hikaru and Isobe, Atsuo and Ando, Yoshinori and Okamoto, Satoru and Kato, Kiyoshi and Yew, Tri Rung and Lin, Chen Bin and Wu, J. Y. and Shuai, Chi Chang and Wu, Shao Hui and Myers, James and Doppler, Klaus and Fujita, Masahiro and Yamazaki, Shunpei}, biburl = {https://www.bibsonomy.org/bibtex/23dc1a3f182daf8de78aa5e7b13df6a75/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {http://dx.doi.org/10.1109/VLSIC.2016.7573504}, interhash = {32b559d48bf830cbeb0fb6220224fb7a}, intrahash = {3dc1a3f182daf8de78aa5e7b13df6a75}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2017-04-08T11:35:33.000+0200}, title = {Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#OnukiUTIAOKYLWS16}, year = 2016 }