%0 Conference Paper %1 conf/date/XingLGM21 %A Xing, Yue %A Lu, Huaixi %A Gupta, Aarti %A Malik, Sharad %B DATE %D 2021 %I IEEE %K dblp %P 1130-1135 %T Leveraging Processor Modeling and Verification for General Hardware Modules. %U http://dblp.uni-trier.de/db/conf/date/date2021.html#XingLGM21 %@ 978-3-9819263-5-4

@inproceedings{conf/date/XingLGM21, added-at = {2023-09-30T00:00:00.000+0200}, author = {Xing, Yue and Lu, Huaixi and Gupta, Aarti and Malik, Sharad}, biburl = {https://www.bibsonomy.org/bibtex/2cb3e0b2da669063037ab114b3f6665a9/dblp}, booktitle = {DATE}, crossref = {conf/date/2021}, ee = {https://doi.org/10.23919/DATE51398.2021.9474194}, interhash = {4faab0cb86f3fdec24c9a0626c995873}, intrahash = {cb3e0b2da669063037ab114b3f6665a9}, isbn = {978-3-9819263-5-4}, keywords = {dblp}, pages = {1130-1135}, publisher = {IEEE}, timestamp = {2024-04-09T12:36:33.000+0200}, title = {Leveraging Processor Modeling and Verification for General Hardware Modules.}, url = {http://dblp.uni-trier.de/db/conf/date/date2021.html#XingLGM21}, year = 2021 }