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Leveraging Processor Modeling and Verification for General Hardware Modules.

, , , and . DATE, page 1130-1135. IEEE, (2021)

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System Level Design: Orthogonolization of Concerns and Platform-Based Design, , , , and . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (December 2000)Certified Timing Verification and the Transition Delay of a Logic Circuit., , , and . DAC, page 549-555. IEEE Computer Society Press, (1992)A formal instruction-level GPU model for scalable verification., , , and . ICCAD, page 130. ACM, (2018)Specification and encoding of transaction interaction properties., , and . Formal Methods Syst. Des., 39 (2): 144-164 (2011)Model checking unbounded concurrent lists., , and . Int. J. Softw. Tools Technol. Transf., 18 (4): 375-391 (2016)Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking., , and . VMCAI, volume 12597 of Lecture Notes in Computer Science, page 325-349. Springer, (2021)INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms., , , and . DAC, page 1-4. IEEE, (2023)Optimization of embedded DSP programs using post-pass data-flow analysis., , , and . ICASSP, page 695-698. IEEE Computer Society, (1997)Exploiting Retiming in a Guided Simulation Based Validation Methodology., , and . CHARME, volume 1703 of Lecture Notes in Computer Science, page 350-353. Springer, (1999)On Solving the Partial MAX-SAT Problem., and . SAT, volume 4121 of Lecture Notes in Computer Science, page 252-265. Springer, (2006)