%0 Conference Paper %1 conf/vlsic/OhsawaKMHTIHOE12 %A Ohsawa, Takashi %A Koike, Hiroki %A Miura, Sadahiko %A Honjo, Hiroaki %A Tokutome, Keiichi %A Ikeda, Shoji %A Hanyu, Takahiro %A Ohno, Hideo %A Endoh, Tetsuo %B VLSIC %D 2012 %I IEEE %K dblp %P 46-47 %T 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#OhsawaKMHTIHOE12 %@ 978-1-4673-0848-9

@inproceedings{conf/vlsic/OhsawaKMHTIHOE12, added-at = {2016-09-27T00:00:00.000+0200}, author = {Ohsawa, Takashi and Koike, Hiroki and Miura, Sadahiko and Honjo, Hiroaki and Tokutome, Keiichi and Ikeda, Shoji and Hanyu, Takahiro and Ohno, Hideo and Endoh, Tetsuo}, biburl = {https://www.bibsonomy.org/bibtex/2765f26f15f5373ab86de48b215ef96f1/dblp}, booktitle = {VLSIC}, crossref = {conf/vlsic/2012}, ee = {http://dx.doi.org/10.1109/VLSIC.2012.6243782}, interhash = {50455dce7ac5272073f61e4e3fddf9bb}, intrahash = {765f26f15f5373ab86de48b215ef96f1}, isbn = {978-1-4673-0848-9}, keywords = {dblp}, pages = {46-47}, publisher = {IEEE}, timestamp = {2016-09-28T11:35:24.000+0200}, title = {1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#OhsawaKMHTIHOE12}, year = 2012 }