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Disambiguation of "Hanyu, Takahiro"

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1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.

, , , , , , , , and . VLSIC, page 46-47. IEEE, (2012)

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Takahiro Kato

Hanyu Ye

Takahiro Moriyama

Takahiro Kirihara

Takahiro Nishiyama

 

Other publications of authors with the same name

Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme., , , and . IEICE Trans. Inf. Syst., 93-D (8): 2080-2088 (2010)Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing., and . IEICE Trans. Electron., 89-C (11): 1598-1604 (2006)Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system., , , and . ISCAS, page 2067-2070. IEEE, (2011)Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link., , , and . APCCAS, page 683-686. IEEE, (2014)High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure., , , , and . ISCAS, page 1-5. IEEE, (2018)Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only)., and . FPGA, page 291. ACM, (2018)NoC-MRAM architecture for memory-based computing: Database-search case study., , , , , , , and . NEWCAS, page 309-312. IEEE, (2017)Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems., , , , and . CoRR, (2023)Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices., , and . IEEE Open J. Circuits Syst., (2021)Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application., , and . Syst. Comput. Jpn., 29 (11): 40-47 (1998)