%0 Conference Paper %1 conf/vlsit/BurrNAOTHMNYDBC23 %A Burr, Geoffrey W. %A Narayanan, Pritish %A Ambrogio, Stefano %A Okazaki, Atsuya %A Tsai, Hsinyu %A Hosokawa, Kohji %A Mackin, Charles %A Nomura, Akiyo %A Yasuda, Takeo %A Demarest, J. %A Brew, Kevin %A Chan, Victor %A Choi, Samuel %A Gordon, T. %A Levin, T. M. %A Friz, Alexander M. %A Ishii, Masatoshi %A Kohda, Yasuteru %A Chen, An %A Fasoli, Andrea %A Luquin, Jose %A Saulnier, Nicole %A Teehan, S. %A Ahsan, Ishtiaq %A Narayanan, Vijay %B VLSI Technology and Circuits %D 2023 %I IEEE %K dblp %P 1-2 %T Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited). %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#BurrNAOTHMNYDBC23 %@ 978-4-86348-806-9

@inproceedings{conf/vlsit/BurrNAOTHMNYDBC23, added-at = {2024-10-06T00:00:00.000+0200}, author = {Burr, Geoffrey W. and Narayanan, Pritish and Ambrogio, Stefano and Okazaki, Atsuya and Tsai, Hsinyu and Hosokawa, Kohji and Mackin, Charles and Nomura, Akiyo and Yasuda, Takeo and Demarest, J. and Brew, Kevin and Chan, Victor and Choi, Samuel and Gordon, T. and Levin, T. M. and Friz, Alexander M. and Ishii, Masatoshi and Kohda, Yasuteru and Chen, An and Fasoli, Andrea and Luquin, Jose and Saulnier, Nicole and Teehan, S. and Ahsan, Ishtiaq and Narayanan, Vijay}, biburl = {https://www.bibsonomy.org/bibtex/2630d2cd58725f67927cdd0e9a76f693e/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2023}, ee = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185411}, interhash = {5aac81aa0791f4ef5cec3e75121664c1}, intrahash = {630d2cd58725f67927cdd0e9a76f693e}, isbn = {978-4-86348-806-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-10-07T09:09:28.000+0200}, title = {Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited).}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#BurrNAOTHMNYDBC23}, year = 2023 }