%0 Conference Paper %1 conf/aspdac/HoSCC13 %A Ho, Yuan-Kai %A Shih, Xin-Wei %A Chang, Yao-Wen %A Cheng, Chung-Kuan %B ASP-DAC %D 2013 %I IEEE %K dblp %P 187-192 %T Layer minimization in escape routing for staggered-pin-array PCBs. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#HoSCC13 %@ 978-1-4673-3029-9

@inproceedings{conf/aspdac/HoSCC13, added-at = {2017-06-01T00:00:00.000+0200}, author = {Ho, Yuan-Kai and Shih, Xin-Wei and Chang, Yao-Wen and Cheng, Chung-Kuan}, biburl = {https://www.bibsonomy.org/bibtex/2750da6ee73de5424d5746a92711a5cc5/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2013}, ee = {https://doi.org/10.1109/ASPDAC.2013.6509594}, interhash = {62060f03b944f7ffbb840a5f75197639}, intrahash = {750da6ee73de5424d5746a92711a5cc5}, isbn = {978-1-4673-3029-9}, keywords = {dblp}, pages = {187-192}, publisher = {IEEE}, timestamp = {2019-10-17T16:44:50.000+0200}, title = {Layer minimization in escape routing for staggered-pin-array PCBs.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#HoSCC13}, year = 2013 }