Inproceedings,
A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.
J. Baek, C. Lee, K. Kim, D. Moon, G. Cha, J. Heo, M. Ahn, D. Kim, J. Song, S. Kwon, J. Kim, K. Kim, J. Ahn, J. Nam, B. Kim, J. Cho, J. Oh, S. Bae, I. Song, S. Hyun, I. Kim, H. Kwon, Y. Sohn, J. Choi, K. Park, and S. Jang.VLSI Circuits, page 147-148. IEEE, (2018)
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- conf/vlsic/BaekLKMCHAKSKKK18
- entry type
- inproceedings
- booktitle
- VLSI Circuits
- year
- 2018
- pages
- 147-148
- publisher
- IEEE
- crossref
- conf/vlsic/2018
- ee
- https://doi.org/10.1109/VLSIC.2018.8502299
- isbn
- 978-1-5386-4214-6
- url
- http://dblp.uni-trier.de/db/conf/vlsic/vlsic2018.html#BaekLKMCHAKSKKK18
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%1 conf/vlsic/BaekLKMCHAKSKKK18
%A Baek, Jin-Hyeok
%A Lee, Chang-Kyo
%A Kim, Kiho
%A Moon, Daesik
%A Cha, Gil-Hoon
%A Heo, Jin-Seok
%A Ahn, Min-Su
%A Kim, Dong-Ju
%A Song, Jae-Joon
%A Kwon, Seokhong
%A Kim, Jongmin
%A Kim, Kyung-Soo
%A Ahn, Jinoh
%A Nam, Jeong-Sik
%A Kim, Byung-Cheol
%A Cho, Jeong-Hyeon
%A Oh, Jeonghoon
%A Bae, Seung-Jun
%A Song, Indal
%A Hyun, Seok-Hun
%A Kim, Ilgweon
%A Kwon, Hyuck-Joon
%A Sohn, Young-Soo
%A Choi, Jung-Hwan
%A Park, Kwang-Il
%A Jang, Seong-Jin
%B VLSI Circuits
%D 2018
%I IEEE
%K dblp
%P 147-148
%T A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.
%U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2018.html#BaekLKMCHAKSKKK18
%@ 978-1-5386-4214-6
@inproceedings{conf/vlsic/BaekLKMCHAKSKKK18,
added-at = {2019-01-25T00:00:00.000+0100},
author = {Baek, Jin-Hyeok and Lee, Chang-Kyo and Kim, Kiho and Moon, Daesik and Cha, Gil-Hoon and Heo, Jin-Seok and Ahn, Min-Su and Kim, Dong-Ju and Song, Jae-Joon and Kwon, Seokhong and Kim, Jongmin and Kim, Kyung-Soo and Ahn, Jinoh and Nam, Jeong-Sik and Kim, Byung-Cheol and Cho, Jeong-Hyeon and Oh, Jeonghoon and Bae, Seung-Jun and Song, Indal and Hyun, Seok-Hun and Kim, Ilgweon and Kwon, Hyuck-Joon and Sohn, Young-Soo and Choi, Jung-Hwan and Park, Kwang-Il and Jang, Seong-Jin},
biburl = {https://www.bibsonomy.org/bibtex/29104915614a493255c0075624c297ce2/dblp},
booktitle = {VLSI Circuits},
crossref = {conf/vlsic/2018},
ee = {https://doi.org/10.1109/VLSIC.2018.8502299},
interhash = {6a98b50f3df8336bd3c4632710e0a00f},
intrahash = {9104915614a493255c0075624c297ce2},
isbn = {978-1-5386-4214-6},
keywords = {dblp},
pages = {147-148},
publisher = {IEEE},
timestamp = {2019-01-26T11:38:15.000+0100},
title = {A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.},
url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2018.html#BaekLKMCHAKSKKK18},
year = 2018
}