( en | de | ru )

 

Disambiguation of "Lee, Chang-Kyo"

Author of the publication

copydeleteadd this publication to your clipboard
A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.

, , , , , , , , , , , , , , , , , , , , , , , , , and . VLSI Circuits, page 147-148. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chang-Kyo Jeong

Chong-Kyo Lee

Kyo-Il Lee

Chang-Uh Lee

Lee Chang Huan

 

Other publications of authors with the same name

Performance Test of LTE-R Railway Wireless Communication at High-Speed (350 km/h) Environments., , , , and . ICUFN, page 637-640. IEEE, (2018)A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction., , , and . CICC, page 1-4. IEEE, (2010)A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface., , , , , , , , , and 6 other author(s). VLSIC, page 182-. IEEE, (2015)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration., , , , , , , , , and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process., , , , , , , , , and 29 other author(s). ISSCC, page 382-384. IEEE, (2020)Design of a 1-Volt and µ-power SARADC for Sensor Network Application., , and . ISCAS, page 3852-3855. IEEE, (2007)Interpretation of Impact-Echo Testing Data from a Fire-Damaged Reinforced Concrete Slab Using a Discrete Layered Concrete Damage Model., , , , and . Sensors, 20 (20): 5838 (2020)Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM., , , , , , , , , and 25 other author(s). A-SSCC, page 153-156. IEEE, (2017)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process., , , , , , , , , and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC., and . IET Circuits Devices Syst., 13 (8): 1277-1283 (2019)