%0 Conference Paper %1 conf/vlsi-dat/ChiouHCHL19 %A Chiou, Lih-Yih %A Huang, Chi-Ray %A Cheng, Chang-Chieh %A Huang, Jing-Yu %A Ling, Wei-Suo %B VLSI-DAT %D 2019 %I IEEE %K dblp %P 1-4 %T A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs. %U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2019.html#ChiouHCHL19 %@ 978-1-7281-0655-7

@inproceedings{conf/vlsi-dat/ChiouHCHL19, added-at = {2019-06-27T00:00:00.000+0200}, author = {Chiou, Lih-Yih and Huang, Chi-Ray and Cheng, Chang-Chieh and Huang, Jing-Yu and Ling, Wei-Suo}, biburl = {https://www.bibsonomy.org/bibtex/251842a923e397742feef2401751d067d/dblp}, booktitle = {VLSI-DAT}, crossref = {conf/vlsi-dat/2019}, ee = {https://doi.org/10.1109/VLSI-DAT.2019.8741606}, interhash = {7029cb1e362c2421f538c9b2a610bf32}, intrahash = {51842a923e397742feef2401751d067d}, isbn = {978-1-7281-0655-7}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2019-06-28T11:43:32.000+0200}, title = {A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs.}, url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2019.html#ChiouHCHL19}, year = 2019 }