%0 Journal Article %1 journals/tvlsi/MurrayLWMWHYCKA20 %A Murray, Kevin E. %A Luu, Jason %A Walker, Matthew J. P. %A McCullough, Conor %A Wang, Sen %A Huda, Safeen %A Yan, Bo %A Chiasson, Charles %A Kent, Kenneth B. %A Anderson, Jason Helge %A Rose, Jonathan %A Betz, Vaughn %D 2020 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 6 %P 1378-1391 %T Optimizing FPGA Logic Block Architectures for Arithmetic. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi28.html#MurrayLWMWHYCKA20 %V 28

@article{journals/tvlsi/MurrayLWMWHYCKA20, added-at = {2020-06-16T00:00:00.000+0200}, author = {Murray, Kevin E. and Luu, Jason and Walker, Matthew J. P. and McCullough, Conor and Wang, Sen and Huda, Safeen and Yan, Bo and Chiasson, Charles and Kent, Kenneth B. and Anderson, Jason Helge and Rose, Jonathan and Betz, Vaughn}, biburl = {https://www.bibsonomy.org/bibtex/22fb92c44c9ea291148374bf722c2a5fa/dblp}, ee = {https://doi.org/10.1109/TVLSI.2020.2965772}, interhash = {72ac62542f4bb9613ea1dfa4d4ef100d}, intrahash = {2fb92c44c9ea291148374bf722c2a5fa}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 6, pages = {1378-1391}, timestamp = {2020-06-17T11:42:53.000+0200}, title = {Optimizing FPGA Logic Block Architectures for Arithmetic.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi28.html#MurrayLWMWHYCKA20}, volume = 28, year = 2020 }