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Optimizing FPGA Logic Block Architectures for Arithmetic.

K. Murray, J. Luu, M. Walker, C. McCullough, S. Wang, S. Huda, B. Yan, C. Chiasson, K. Kent, J. Anderson, J. Rose, and V. Betz. IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1378-1391 (2020)

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Ian Jason

Luu Quang Minh

Luu Dat Thuyet

Luu Duan

Keurcien Luu

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VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling.K. Murray, O. Petelin, S. Zhong, J. Wang, M. Eldafrawy, J. Legault, E. Sha, A. Graham, J. Wu, M. Walker and 5 other author(s). ACM Trans. Reconfigurable Technol. Syst., 13 (2): 9:1-9:55 (2020)The VTR project: architecture and CAD for FPGAs from verilog to routing.J. Rose, J. Luu, C. Yu, O. Densmore, J. Goeders, A. Somerville, K. Kent, P. Jamieson, and J. Anderson. FPGA, page 77-86. ACM, (2012)FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy.J. Luu, K. Redmond, W. Lo, P. Chow, L. Lilge, and J. Rose. FCCM, page 157-164. IEEE Computer Society, (2009)Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect.J. Luu, J. Anderson, and J. Rose. FPGA, page 227-236. ACM, (2011)Hybrid LUT/Multiplexer FPGA Logic Architectures.S. Chin, J. Luu, S. Huda, and J. Anderson. IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1280-1292 (2016)VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, W. Fang, and J. Rose. FPGA, page 133-142. ACM, (2009)Towards interconnect-adaptive packing for FPGAs.J. Luu, J. Rose, and J. Anderson. FPGA, page 21-30. ACM, (2014)From Quartus to VPR: Converting HDL to BLIF with the Titan flow.K. Murray, S. Whitty, S. Liu, J. Luu, and V. Betz. FPL, page 1. IEEE, (2013)Optimizing FPGA Logic Block Architectures for Arithmetic.K. Murray, J. Luu, M. Walker, C. McCullough, S. Wang, S. Huda, B. Yan, C. Chiasson, K. Kent, J. Anderson and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1378-1391 (2020)On Hard Adders and Carry Chains in FPGAs.J. Luu, C. McCullough, S. Wang, S. Huda, B. Yan, C. Chiasson, K. Kent, J. Anderson, J. Rose, and V. Betz. FCCM, page 52-59. IEEE Computer Society, (2014)

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Optimizing FPGA Logic Block Architectures for Arithmetic.

Please choose a person to relate this publication to

Ian Jason

Luu Quang Minh

Luu Dat Thuyet

Luu Duan

Keurcien Luu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Luu, Jason"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Optimizing FPGA Logic Block Architectures for Arithmetic.

Please choose a person to relate this publication to

Ian Jason

Luu Quang Minh

Luu Dat Thuyet

Luu Duan

Keurcien Luu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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APA
Chicago
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Optimizing FPGA Logic Block Architectures for Arithmetic.