%0 Conference Paper %1 conf/glvlsi/AgrawalAR96 %A Agrawal, Nidhi %A Agarwal, Parul %A Ravikumar, C. P. %B Great Lakes Symposium on VLSI %D 1996 %I IEEE Computer Society %K dblp %P 220- %T Efficient Delay Test Generation for Modular Circuits. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1996.html#AgrawalAR96 %@ 0-8186-7502-0

@inproceedings{conf/glvlsi/AgrawalAR96, added-at = {2023-03-24T00:00:00.000+0100}, author = {Agrawal, Nidhi and Agarwal, Parul and Ravikumar, C. P.}, biburl = {https://www.bibsonomy.org/bibtex/2f3b606f4659db4830bb727671f234877/dblp}, booktitle = {Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/1996}, ee = {http://dl.acm.org/citation.cfm?id=875777}, interhash = {817186ef3dc57b65ef328037aa6b2401}, intrahash = {f3b606f4659db4830bb727671f234877}, isbn = {0-8186-7502-0}, keywords = {dblp}, pages = {220-}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T16:23:26.000+0200}, title = {Efficient Delay Test Generation for Modular Circuits.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1996.html#AgrawalAR96}, year = 1996 }