%0 Conference Paper %1 conf/iscas/TsaiKGL10 %A Tsai, Chia-Chun %A Kuo, Chung-Chieh %A Gu, Lin-Jeng %A Lee, Trong-Yen %B ISCAS %D 2010 %I IEEE %K dblp %P 3413-3416 %T Double-via insertion enhanced X-architecture clock routing for reliability. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2010.html#TsaiKGL10 %@ 978-1-4244-5309-2

@inproceedings{conf/iscas/TsaiKGL10, added-at = {2011-04-14T00:00:00.000+0200}, author = {Tsai, Chia-Chun and Kuo, Chung-Chieh and Gu, Lin-Jeng and Lee, Trong-Yen}, biburl = {https://www.bibsonomy.org/bibtex/2075e8c636ae74d30f3156e906b694d62/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/2010}, ee = {http://dx.doi.org/10.1109/ISCAS.2010.5537863}, interhash = {824082b5c0b7f4f3c71ce6adcd7a7ff1}, intrahash = {075e8c636ae74d30f3156e906b694d62}, isbn = {978-1-4244-5309-2}, keywords = {dblp}, pages = {3413-3416}, publisher = {IEEE}, timestamp = {2016-05-21T12:21:27.000+0200}, title = {Double-via insertion enhanced X-architecture clock routing for reliability.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2010.html#TsaiKGL10}, year = 2010 }