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Disambiguation of "Tsai, Chia-Chun"

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Double-via insertion enhanced X-architecture clock routing for reliability.

, , , and . ISCAS, page 3413-3416. IEEE, (2010)

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Chia-Chun Lu

Chia-Chun Liang

Chia-chun Gu

Yu-Chun Tsai

Yin-chun Tsai-Stürenberg

 

Other publications of authors with the same name

The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B., , and . Journal of Circuits, Systems, and Computers, 20 (8): 1637-1658 (2011)Low Complexity Digit-Serial Multiplier over GF(2^m) Using Karatsuba Technology., , , , and . CISIS, page 461-466. IEEE Computer Society, (2013)Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems., , , and . J. Inf. Sci. Eng., 26 (4): 1289-1305 (2010)Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration., , and . Integr., 44 (1): 87-101 (2011)GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (1): 365-374 (2008)Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (2): 706-716 (2011)Zero-Skew Driven for RLC Clock Tree Construction in SoC., , , , and . ICITA (1), page 561-566. IEEE Computer Society, (2005)Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion., , and . ICICIC (2), page 515-518. IEEE Computer Society, (2006)A Threshold-based Scheduling and Power Control Design on IMT-2020 Evaluation., , , , and . APSIPA ASC, page 1889-1894. IEEE, (2021)Antenna Violation Avoidance/Fixing for X-clock routing., , , and . ISQED, page 508-514. IEEE, (2010)