%0 Journal Article %1 journals/tcasII/HeSWWTZLLWL22 %A He, Zhen %A Shi, Cong %A Wang, Tengxiao %A Wang, Ying %A Tian, Min %A Zhou, Xichuan %A Li, Ping %A Liu, Liyuan %A Wu, Nanjian %A Luo, Gang %D 2022 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 3 %P 1657-1661 %T A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning. %U http://dblp.uni-trier.de/db/journals/tcasII/tcasII69.html#HeSWWTZLLWL22 %V 69

@article{journals/tcasII/HeSWWTZLLWL22, added-at = {2023-10-12T00:00:00.000+0200}, author = {He, Zhen and Shi, Cong and Wang, Tengxiao and Wang, Ying and Tian, Min and Zhou, Xichuan and Li, Ping and Liu, Liyuan and Wu, Nanjian and Luo, Gang}, biburl = {https://www.bibsonomy.org/bibtex/27b08c1040033ac6c59d1f23d3da327b6/dblp}, ee = {https://doi.org/10.1109/TCSII.2021.3117699}, interhash = {827b412a45827e60abdaa6876b8cf622}, intrahash = {7b08c1040033ac6c59d1f23d3da327b6}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, number = 3, pages = {1657-1661}, timestamp = {2024-04-08T16:53:08.000+0200}, title = {A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.}, url = {http://dblp.uni-trier.de/db/journals/tcasII/tcasII69.html#HeSWWTZLLWL22}, volume = 69, year = 2022 }