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A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.

Z. He, C. Shi, T. Wang, Y. Wang, M. Tian, X. Zhou, P. Li, L. Liu, N. Wu, and G. Luo. IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1657-1661 (2022)

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Jinglan Wu

Recovery of citric acid from fermentation broth using simulated moving bed technology: = Reinigung von Zitronensäure aus Fermentationslösung durch kontinuierliche ChromatographieJ. Wu. Uni Erlangen-Nürnberg, (2009)

Jinjin Wu

Yinghua Wu

Changzhu Wu

Haiyan Wu

Other publications of authors with the same name

Terahertz detector for imaging in 180-nm standard CMOS process.Z. yang Liu, L. Liu, Z. Zhang, J. Liu, and N. Wu. Sci. China Inf. Sci., 60 (8): 82401 (2017)A LO-leakage auto-calibrated CMOS IEEE802.11b/g WLAN transceiver.H. Wang, G. Shou, and N. Wu. ISCAS, page 3912-3915. IEEE, (2007)A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique.Z. Zhang, L. Liu, P. Feng, and N. Wu. IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 929-941 (2017)An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips.L. Chen, C. Shi, J. He, J. Yu, H. Wang, J. Lu, L. Liu, N. Wu, and M. Tian. IEEE Trans. Circuits Syst. I Regul. Pap., 70 (11): 4249-4259 (November 2023)A Compact High-Quality Image Demosaicking Neural Network for Edge-Computing Devices.S. Wang, M. Zhao, R. Dou, S. Yu, L. Liu, and N. Wu. Sensors, 21 (9): 3265 (2021)A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology.T. Fang, M. Liu, L. Liu, Z. Cai, R. Dou, P. Feng, N. Qi, Z. Zhang, J. Liu, and N. Wu. ICTA, page 259-260. IEEE, (2021)Floorplanning and Power/Ground Network Design for A Programmable Vision Chip.H. Xu, S. Wei, N. Qi, P. Wu, J. Liu, N. Wu, L. Liu, and S. Yu. ICTA, page 184-185. IEEE, (2022)A High-speed Low-cost CNN Inference Accelerator for Depthwise Separable Convolution.Y. Lin, R. Li, W. He, X. Zhou, J. He, P. Li, Y. Jiang, L. Liu, N. Wu, and C. Shi. ICTA, page 63-64. IEEE, (2020)A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE.Z. Zhang, Z. Zhang, Y. Chen, G. Wang, X. Shen, N. Qi, G. Li, S. Yu, J. Liu, N. Wu and 1 other author(s). ESSCIRC, page 177-180. IEEE, (2023)A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.Z. Zhang, X. Shen, Z. Zhang, G. Li, N. Qi, J. Liu, Y. Chen, N. Wu, and L. Liu. ISSCC, page 86-87. IEEE, (2023)

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Disambiguation of "Wu, Nanjian"

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A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.

Please choose a person to relate this publication to

Jinglan Wu

Jinjin Wu

Yinghua Wu

Changzhu Wu

Haiyan Wu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wu, Nanjian"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.

Please choose a person to relate this publication to

Jinglan Wu

Jinjin Wu

Yinghua Wu

Changzhu Wu

Haiyan Wu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.