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%0 Conference Paper
%1 conf/iscas/BadarogluPWDGM07
%A Badaroglu, Mustafa
%A der Plas, Geert Van
%A Wambacq, Piet
%A Donnay, Stéphane
%A Gielen, Georges G. E.
%A Man, Hugo De
%B ISCAS
%D 2007
%I IEEE
%K dblp
%P 2938-2941
%T Scalable Gate-Level Models for Power and Timing Analysis.
%U http://dblp.uni-trier.de/db/conf/iscas/iscas2007.html#BadarogluPWDGM07
%@ 1-4244-0921-7
@inproceedings{conf/iscas/BadarogluPWDGM07,
added-at = {2018-11-02T00:00:00.000+0100},
author = {Badaroglu, Mustafa and der Plas, Geert Van and Wambacq, Piet and Donnay, Stéphane and Gielen, Georges G. E. and Man, Hugo De},
biburl = {https://www.bibsonomy.org/bibtex/212c4b1c991aa4abfa36945ee5589790a/dblp},
booktitle = {ISCAS},
crossref = {conf/iscas/2007},
ee = {https://doi.org/10.1109/ISCAS.2007.377865},
interhash = {83738bb4da07445e5c9a3b9e6a84321c},
intrahash = {12c4b1c991aa4abfa36945ee5589790a},
isbn = {1-4244-0921-7},
keywords = {dblp},
pages = {2938-2941},
publisher = {IEEE},
timestamp = {2018-11-03T15:19:54.000+0100},
title = {Scalable Gate-Level Models for Power and Timing Analysis.},
url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2007.html#BadarogluPWDGM07},
year = 2007
}