%0 Conference Paper %1 conf/vlsid/FlaniganACLTP07 %A Flanigan, Edward %A Adapa, Rajsekhar %A Cui, Hailong %A Laisne, Michael %A Tragoudas, Spyros %A Petrov, Tsvetomir %B VLSI Design %D 2007 %I IEEE Computer Society %K dblp %P 805-812 %T Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#FlaniganACLTP07 %@ 0-7695-2762-0

@inproceedings{conf/vlsid/FlaniganACLTP07, added-at = {2023-03-24T00:00:00.000+0100}, author = {Flanigan, Edward and Adapa, Rajsekhar and Cui, Hailong and Laisne, Michael and Tragoudas, Spyros and Petrov, Tsvetomir}, biburl = {https://www.bibsonomy.org/bibtex/22244e360ea1dde0361c0c37cabb13e6d/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2007}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2007.86}, interhash = {86d535477570e2495f1bc7faa684f61c}, intrahash = {2244e360ea1dde0361c0c37cabb13e6d}, isbn = {0-7695-2762-0}, keywords = {dblp}, pages = {805-812}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:09.000+0200}, title = {Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#FlaniganACLTP07}, year = 2007 }