%0 Conference Paper %1 conf/vlsi-dat/ChenCH14 %A Chen, Yi-Hang %A Chen, Yi-Ting %A Huang, Juinn-Dar %B VLSI-DAT %D 2014 %I IEEE %K dblp %P 1-4 %T Two-staged parallel layer-aware partitioning for 3D designs. %U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2014.html#ChenCH14

@inproceedings{conf/vlsi-dat/ChenCH14, added-at = {2020-06-15T00:00:00.000+0200}, author = {Chen, Yi-Hang and Chen, Yi-Ting and Huang, Juinn-Dar}, biburl = {https://www.bibsonomy.org/bibtex/2b0e1a5b478f530d39411f21916f8007e/dblp}, booktitle = {VLSI-DAT}, crossref = {conf/vlsi-dat/2014}, ee = {https://doi.org/10.1109/VLSI-DAT.2014.6834861}, interhash = {8758294fc6fc233cbcb88ae7149dc7e9}, intrahash = {b0e1a5b478f530d39411f21916f8007e}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2020-06-16T12:54:11.000+0200}, title = {Two-staged parallel layer-aware partitioning for 3D designs.}, url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2014.html#ChenCH14}, year = 2014 }