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Disambiguation of "Huang, Juinn-Dar"

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Two-staged parallel layer-aware partitioning for 3D designs.

, , and . VLSI-DAT, page 1-4. IEEE, (2014)

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Shaul Dar

Cheng-Dar Yue

Altaf Ahmad Dar

Maureen Dar Iang

Feiqing Huang

 

Other publications of authors with the same name

Cycle-time-aware sequential way-access set-associative cache for low energy consumption., , and . APCCAS, page 854-857. IEEE, (2008)Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (9): 1429-1440 (2015)Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (4): 816-829 (2020)Latency-optimization synthesis with module selection for digital microfluidic biochips., , and . SoCC, page 159-164. IEEE, (2013)Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration., , and . SoCC, page 316-317. IEEE, (2013)Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (4): 614-627 (2017)A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses., , , and . ASP-DAC, page 165-170. IEEE Computer Society, (2007)Fault Dictionary Size Reduction for Million-Gate Large Circuits., and . ASP-DAC, page 829-834. IEEE Computer Society, (2007)Layer-Aware Design Partitioning for Vertical Interconnect Minimization., , and . ISVLSI, page 144-149. IEEE Computer Society, (2011)Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family., and . ISVLSI, page 369-370. IEEE Computer Society, (2011)