%0 Conference Paper %1 conf/vlsic/OkumuraYHN19 %A Okumura, Shunsuke %A Yabuuchi, Makoto %A Hijioka, Kenichiro %A Nose, Koichi %B VLSI Circuits %D 2019 %I IEEE %K dblp %P 248- %T A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#OkumuraYHN19 %@ 978-4-86348-720-8

@inproceedings{conf/vlsic/OkumuraYHN19, added-at = {2019-08-05T00:00:00.000+0200}, author = {Okumura, Shunsuke and Yabuuchi, Makoto and Hijioka, Kenichiro and Nose, Koichi}, biburl = {https://www.bibsonomy.org/bibtex/24e211db3a49d09fe69dce8dc76ca7a03/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2019}, ee = {https://doi.org/10.23919/VLSIC.2019.8778187}, interhash = {92664b8d5e060c2ab63ff421ceed14a6}, intrahash = {4e211db3a49d09fe69dce8dc76ca7a03}, isbn = {978-4-86348-720-8}, keywords = {dblp}, pages = {248-}, publisher = {IEEE}, timestamp = {2019-08-06T11:40:26.000+0200}, title = {A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#OkumuraYHN19}, year = 2019 }