%0 Conference Paper %1 conf/vlsid/KajitaniTAN00 %A Kajitani, Yoji %A Takahashi, Atsushi %A Azegami, Kengo R. %A Nakatake, Shigetoshi %B VLSI Design %D 2000 %I IEEE Computer Society %K dblp %P 11 %T Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#KajitaniTAN00 %@ 0-7695-0487-6

@inproceedings{conf/vlsid/KajitaniTAN00, added-at = {2023-06-26T00:00:00.000+0200}, author = {Kajitani, Yoji and Takahashi, Atsushi and Azegami, Kengo R. and Nakatake, Shigetoshi}, biburl = {https://www.bibsonomy.org/bibtex/26eae98c9469fb586ef723a76c4a1bf7e/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2000}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812577}, interhash = {93cdeb480c0faf26b6df848944f6e298}, intrahash = {6eae98c9469fb586ef723a76c4a1bf7e}, isbn = {0-7695-0487-6}, keywords = {dblp}, pages = 11, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:19:01.000+0200}, title = {Partition, Packing and Clock Distribution-A New Paradigm of Physical Design.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#KajitaniTAN00}, year = 2000 }