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Partition, Packing and Clock Distribution-A New Paradigm of Physical Design.

, , , и . VLSI Design, стр. 11. IEEE Computer Society, (2000)

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Yoji Ito

 

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Order of Channels for Safe Routing and Optimal Compaction of Routing Area.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2 (4): 293-300 (1983)Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules., , и . ASP-DAC, стр. 571-576. IEEE, (1998)The Oct-Touched Tile: A New Architecture for Shape-Based Routing., , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (2): 448-455 (2006)A matroid generalization of theorems of Lewin and Gallai., и . Discret. Appl. Math., 9 (2): 213-216 (1984)New Approximation Results on Graph Matching and related Problems., , и . WG, том 903 из Lecture Notes in Computer Science, стр. 343-358. Springer, (1994)Equidistance routing in high-speed VLSI layout design., , , и . ACM Great Lakes Symposium on VLSI, стр. 220-223. ACM, (2004)Adaptive Porting of Analog IPs with Reusable Conservative Properties., , , , , и . ISVLSI, стр. 18-23. IEEE Computer Society, (2006)Optimal single hop multiple bus networks., , и . ISCAS, стр. 2541-2544. IEEE, (1993)Chip size estimation based on wiring area., , , и . APCCAS (2), стр. 113-118. IEEE, (2002)Mixed-Searching and Proper-Path-Width., , и . ISA, том 557 из Lecture Notes in Computer Science, стр. 61-71. Springer, (1991)