%0 Conference Paper %1 conf/iscas/ZhugeXS02 %A Zhuge, Qingfeng %A Xiao, Bin %A Sha, Edwin Hsing-Mean %B ISCAS (5) %D 2002 %I IEEE %K dblp %P 469-472 %T Performance optimization of multiple memory architectures for DSP. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2002-5.html#ZhugeXS02 %@ 0-7803-7448-7

@inproceedings{conf/iscas/ZhugeXS02, added-at = {2016-05-20T00:00:00.000+0200}, author = {Zhuge, Qingfeng and Xiao, Bin and Sha, Edwin Hsing-Mean}, biburl = {https://www.bibsonomy.org/bibtex/24cf551c645e4eb6d80302d4853e831a8/dblp}, booktitle = {ISCAS (5)}, crossref = {conf/iscas/2002}, ee = {http://dx.doi.org/10.1109/ISCAS.2002.1010742}, interhash = {a0111ac3844c0f417d4e7c52353ee0ba}, intrahash = {4cf551c645e4eb6d80302d4853e831a8}, isbn = {0-7803-7448-7}, keywords = {dblp}, pages = {469-472}, publisher = {IEEE}, timestamp = {2016-05-21T12:03:45.000+0200}, title = {Performance optimization of multiple memory architectures for DSP.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2002-5.html#ZhugeXS02}, year = 2002 }