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Performance optimization of multiple memory architectures for DSP.

Q. Zhuge, B. Xiao, and E. Sha. ISCAS (5), page 469-472. IEEE, (2002)

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Realistic Task Parallelization of the H.264 Decoding Algorithm for Multiprocessors.X. Lin, W. Liu, C. Xiao, J. Dai, X. Luo, D. Zhang, D. Liu, K. Wu, Q. Zhuge, and E. Sha. HPCC/CSS/ICESS, page 871-874. IEEE, (2015)User Experience Enhanced Task Scheduling and Processor Frequency Scaling for Energy-Sensitive Mobile Devices.J. Dai, W. Liu, X. Lin, Y. Ye, C. Xiao, K. Wu, Q. Zhuge, and E. Sha. HPCC/CSS/ICESS, page 941-944. IEEE, (2015)Efficient task assignment and scheduling for MPSoC DSPS with VS-SPM considering concurrent accesses through data allocation.S. Gu, Q. Zhuge, J. Hu, J. Yi, and E. Sha. ICASSP, page 2615-2619. IEEE, (2013)General loop fusion technique for nested loops considering timing and code size.M. Liu, Q. Zhuge, Z. Shao, and E. Sha. CASES, page 190-201. ACM, (2004)Optimal scheduling to minimize non-volatile memory access time with hardware cache.W. Tseng, C. Xue, Q. Zhuge, J. Hu, and E. Sha. VLSI-SoC, page 131-136. IEEE, (2010)Performance optimization of multiple memory architectures for DSP.Q. Zhuge, B. Xiao, and E. Sha. ISCAS (5), page 469-472. IEEE, (2002)An Integrated Framework of Design Optimization and Space Minimization for DSP applications.Q. Zhuge, E. Sha, and C. Chantrapornchai. ISCAS (5), page 601-604. IEEE, (2003)An Empirical Study of NVM-based File System.H. Duan, L. Shi, Q. Zhuge, E. Sha, C. Li, and Y. Liang. NVMSA, page 1-6. IEEE, (2021)Architectural Exploration on Racetrack Memories.R. Xu, E. Sha, Q. Zhuge, L. Shi, and S. Gu. SoCC, page 31-36. IEEE, (2020)Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors.J. Hu, Q. Zhuge, C. Xue, W. Tseng, and E. Sha. ACM Trans. Embed. Comput. Syst., 13 (4): 79:1-79:25 (2014)

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Performance optimization of multiple memory architectures for DSP.

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Disambiguation of "Zhuge, Qingfeng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Performance optimization of multiple memory architectures for DSP.

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Performance optimization of multiple memory architectures for DSP.