Inproceedings,
BEOL Interconnect Innovation: Materials, Process and Systems Co-optimization for 3nm Node and Beyond.
G. Thareja, A. Pal, X. Wang, S. Dag, S. You, S. Sharma, Q. Zhu, C. Cervantes, S. Hwang, M. Spuller, B. Ng, P. Kumar, N. Tam, M. Gage, S. Deshpande, Z. Wu, A. Jansen, L. Dey, F. Chen, X. Xie, K. Kashefizadeh, V. Reddy, A. Lo, Z. Chen, S. Huey, J. Tang, H. Ren, M. Naik, B. Brown, S. Kesapragada, B. Ayyagari-Sangamalli, E. Bazizi, and X. Tang.VLSI Technology and Circuits, page 1-2. IEEE, (2023)
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- conf/vlsit/TharejaPWDYSZCH23
- entry type
- inproceedings
- booktitle
- VLSI Technology and Circuits
- year
- 2023
- pages
- 1-2
- publisher
- IEEE
- crossref
- conf/vlsit/2023
- ee
- https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185299
- isbn
- 978-4-86348-806-9
- url
- http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#TharejaPWDYSZCH23
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%1 conf/vlsit/TharejaPWDYSZCH23
%A Thareja, Gaurav
%A Pal, Ashish
%A Wang, Xingye
%A Dag, Sefa
%A You, Shi
%A Sharma, Shashank
%A Zhu, Qing
%A Cervantes, Carmen L.
%A Hwang, Shinjae
%A Spuller, Matthew
%A Ng, Ben
%A Kumar, Pradeep S.
%A Tam, Norman
%A Gage, Max
%A Deshpande, Sameer
%A Wu, Zhiyuan
%A Jansen, Alexander
%A Dey, Liton
%A Chen, Feng
%A Xie, Xianjin
%A Kashefizadeh, Keyvan
%A Reddy, Vinod
%A Lo, Andy
%A Chen, Zhebo
%A Huey, Sidney
%A Tang, Jianshe
%A Ren, He
%A Naik, Mehul
%A Brown, Brian
%A Kesapragada, Sree
%A Ayyagari-Sangamalli, Buvna
%A Bazizi, El Mehdi
%A Tang, Xianmin
%B VLSI Technology and Circuits
%D 2023
%I IEEE
%K dblp
%P 1-2
%T BEOL Interconnect Innovation: Materials, Process and Systems Co-optimization for 3nm Node and Beyond.
%U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#TharejaPWDYSZCH23
%@ 978-4-86348-806-9
@inproceedings{conf/vlsit/TharejaPWDYSZCH23,
added-at = {2023-07-28T00:00:00.000+0200},
author = {Thareja, Gaurav and Pal, Ashish and Wang, Xingye and Dag, Sefa and You, Shi and Sharma, Shashank and Zhu, Qing and Cervantes, Carmen L. and Hwang, Shinjae and Spuller, Matthew and Ng, Ben and Kumar, Pradeep S. and Tam, Norman and Gage, Max and Deshpande, Sameer and Wu, Zhiyuan and Jansen, Alexander and Dey, Liton and Chen, Feng and Xie, Xianjin and Kashefizadeh, Keyvan and Reddy, Vinod and Lo, Andy and Chen, Zhebo and Huey, Sidney and Tang, Jianshe and Ren, He and Naik, Mehul and Brown, Brian and Kesapragada, Sree and Ayyagari-Sangamalli, Buvna and Bazizi, El Mehdi and Tang, Xianmin},
biburl = {https://www.bibsonomy.org/bibtex/2bd35d62784f96786572f0b18aac1501b/dblp},
booktitle = {VLSI Technology and Circuits},
crossref = {conf/vlsit/2023},
ee = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185299},
interhash = {aad983a22efcb53e03ea3b133420b939},
intrahash = {bd35d62784f96786572f0b18aac1501b},
isbn = {978-4-86348-806-9},
keywords = {dblp},
pages = {1-2},
publisher = {IEEE},
timestamp = {2024-04-09T19:13:01.000+0200},
title = {BEOL Interconnect Innovation: Materials, Process and Systems Co-optimization for 3nm Node and Beyond.},
url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#TharejaPWDYSZCH23},
year = 2023
}