%0 Conference Paper %1 conf/vlsic/ChaeCLCYNHLLSSL19 %A Chae, Kwanyeob %A Choi, JongRyun %A Lee, Hyungkwon %A Choi, Jinho %A Yi, Shinyoung %A Nam, Yoonjee %A Hwang, Sangyun %A Lee, Joohyung %A Lee, Won %A Seong, Kihwan %A Shin, Joohee %A Lee, Soo-Min %A Ko, Seokkyun %A Oh, Jihun %A Koo, Billy %A Park, Sanghune %A Shin, Jongshin %A Ko, Hyungjong %B VLSI Circuits %D 2019 %I IEEE %K dblp %P 96- %T An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#ChaeCLCYNHLLSSL19 %@ 978-4-86348-720-8

@inproceedings{conf/vlsic/ChaeCLCYNHLLSSL19, added-at = {2019-08-05T00:00:00.000+0200}, author = {Chae, Kwanyeob and Choi, JongRyun and Lee, Hyungkwon and Choi, Jinho and Yi, Shinyoung and Nam, Yoonjee and Hwang, Sangyun and Lee, Joohyung and Lee, Won and Seong, Kihwan and Shin, Joohee and Lee, Soo-Min and Ko, Seokkyun and Oh, Jihun and Koo, Billy and Park, Sanghune and Shin, Jongshin and Ko, Hyungjong}, biburl = {https://www.bibsonomy.org/bibtex/2f3b0b10995ccb8a11c7c891ee20a9439/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2019}, ee = {https://doi.org/10.23919/VLSIC.2019.8777959}, interhash = {ad3ed3dbef1090b1d83baa8cbfec0259}, intrahash = {f3b0b10995ccb8a11c7c891ee20a9439}, isbn = {978-4-86348-720-8}, keywords = {dblp}, pages = {96-}, publisher = {IEEE}, timestamp = {2019-08-06T11:40:26.000+0200}, title = {An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#ChaeCLCYNHLLSSL19}, year = 2019 }