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Disambiguation of "Seong, Kihwan"

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An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.

, , , , , , , , , , , , , , , , , and . VLSI Circuits, page 96-. IEEE, (2019)

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Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

Seong Lee

 

Other publications of authors with the same name

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques., , , , , , , , , and 6 other author(s). ISSCC, page 114-115. IEEE, (2023)8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz., , , , , , and . ISSCC, page 154-155. IEEE, (2017)All-synthesizable transmitter driver and data recovery circuit for USB2.0 interface., , , , and . ISOCC, page 63-64. IEEE, (2016)All-synthesizable 6Gbps voltage-mode transmitter for serial link., , , , and . A-SSCC, page 245-248. IEEE, (2016)22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique., , , , , , , , , and 6 other author(s). ISSCC, page 338-340. IEEE, (2020)An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme., , , , , , , , , and 8 other author(s). VLSI Circuits, page 96-. IEEE, (2019)13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets., , , , , , , , , and 7 other author(s). ISSCC, page 250-252. IEEE, (2024)