Article,
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.
Y. Ryu, S. Ahn, J. Lee, J. Park, Y. Kim, H. Kim, Y. Song, H. Cho, S. Cho, S. Song, H. Lee, U. Shin, J. Ahn, J. Ryu, S. Lee, K. Lim, J. Lee, J. Park, J. Jeong, S. Jo, D. Cho, S. Kim, M. Lee, H. Kim, M. Kim, J. Kim, J. Kim, H. Kang, M. Lee, S. Kim, Y. Kwon, Y. Byun, K. Lee, S. Park, J. Youn, M. Kim, K. Sohn, S. Hwang, and J. Lee.IEEE J. Solid State Circuits, 58 (4): 1051-1061 (2023)
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- IEEE J. Solid State Circuits
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- 1051-1061
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- 58
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- https://doi.org/10.1109/JSSC.2022.3232096
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%1 journals/jssc/RyuALPKKSCCSLSA23
%A Ryu, Yesin
%A Ahn, Sung-Gi
%A Lee, Jae Hoon
%A Park, Jaewon
%A Kim, Yong-Ki
%A Kim, Hyochang
%A Song, Yeong Geol
%A Cho, Han-Won
%A Cho, Sunghye
%A Song, Seung Ho
%A Lee, Haesuk
%A Shin, Useung
%A Ahn, Jonghyun
%A Ryu, Je-Min
%A Lee, Suk Han
%A Lim, Kyounghwan
%A Lee, Jungyu
%A Park, Jeong Hoan
%A Jeong, Jae-Seung
%A Jo, Sunghwan
%A Cho, Dajung
%A Kim, Sooyoung
%A Lee, Minsu
%A Kim, Hyunho
%A Kim, Minhwan
%A Kim, Jae San
%A Kim, Jinah
%A Kang, Hyun Gil
%A Lee, Myung-Kyu
%A Kim, Sung-Rae
%A Kwon, Young-Cheon
%A Byun, Young-Yong
%A Lee, Kijun
%A Park, Sangkil
%A Youn, Jaeyoun
%A Kim, Myeong-O.
%A Sohn, Kyomin
%A Hwang, SangJoon
%A Lee, JooYoung
%D 2023
%J IEEE J. Solid State Circuits
%K dblp
%N 4
%P 1051-1061
%T A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc58.html#RyuALPKKSCCSLSA23
%V 58
@article{journals/jssc/RyuALPKKSCCSLSA23,
added-at = {2023-04-16T00:00:00.000+0200},
author = {Ryu, Yesin and Ahn, Sung-Gi and Lee, Jae Hoon and Park, Jaewon and Kim, Yong-Ki and Kim, Hyochang and Song, Yeong Geol and Cho, Han-Won and Cho, Sunghye and Song, Seung Ho and Lee, Haesuk and Shin, Useung and Ahn, Jonghyun and Ryu, Je-Min and Lee, Suk Han and Lim, Kyounghwan and Lee, Jungyu and Park, Jeong Hoan and Jeong, Jae-Seung and Jo, Sunghwan and Cho, Dajung and Kim, Sooyoung and Lee, Minsu and Kim, Hyunho and Kim, Minhwan and Kim, Jae San and Kim, Jinah and Kang, Hyun Gil and Lee, Myung-Kyu and Kim, Sung-Rae and Kwon, Young-Cheon and Byun, Young-Yong and Lee, Kijun and Park, Sangkil and Youn, Jaeyoun and Kim, Myeong-O. and Sohn, Kyomin and Hwang, SangJoon and Lee, JooYoung},
biburl = {https://www.bibsonomy.org/bibtex/289277ae1901cc73b3211412e4d7b5724/dblp},
ee = {https://doi.org/10.1109/JSSC.2022.3232096},
interhash = {b0141a179f437324773797ebb31a56b5},
intrahash = {89277ae1901cc73b3211412e4d7b5724},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 4,
pages = {1051-1061},
timestamp = {2024-04-08T10:44:19.000+0200},
title = {A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc58.html#RyuALPKKSCCSLSA23},
volume = 58,
year = 2023
}