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A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , и . IEEE J. Solid State Circuits, 58 (4): 1051-1061 (2023)

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Jaewon Ahn

Jaewon Song

Jinhyung Park

Kwan Park

Shinja Park

 

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