%0 Conference Paper %1 conf/rsp/BarzegarSA14 %A Barzegar, Ali %A Saboori, Ehsan %A Abdi, Samar %B RSP %D 2014 %I IEEE %K dblp %P 86-92 %T DRAC: a dynamically reconfigurable active L1 cache model for hybrid prototyping of multicore embedded systems. %U http://dblp.uni-trier.de/db/conf/rsp/rsp2014.html#BarzegarSA14

@inproceedings{conf/rsp/BarzegarSA14, added-at = {2014-12-03T00:00:00.000+0100}, author = {Barzegar, Ali and Saboori, Ehsan and Abdi, Samar}, biburl = {https://www.bibsonomy.org/bibtex/25d08cbd59b9dddbc6a88f51e615ce3ea/dblp}, booktitle = {RSP}, crossref = {conf/rsp/2014}, ee = {http://dx.doi.org/10.1109/RSP.2014.6966897}, interhash = {b09cf167a03280fff4a0a8717eb811b7}, intrahash = {5d08cbd59b9dddbc6a88f51e615ce3ea}, keywords = {dblp}, pages = {86-92}, publisher = {IEEE}, timestamp = {2015-06-19T22:23:06.000+0200}, title = {DRAC: a dynamically reconfigurable active L1 cache model for hybrid prototyping of multicore embedded systems.}, url = {http://dblp.uni-trier.de/db/conf/rsp/rsp2014.html#BarzegarSA14}, year = 2014 }