Inproceedings,
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.
W. Neto, V. Possani, F. Marranghello, J. Matos, A. Reis, and R. Ribas.SBCCI, page 1-6. IEEE, (2018)
Meta data
- BibTeX key
- conf/sbcci/NetoPMMRR18
- entry type
- inproceedings
- booktitle
- SBCCI
- year
- 2018
- pages
- 1-6
- publisher
- IEEE
- crossref
- conf/sbcci/2018
- ee
- https://doi.org/10.1109/SBCCI.2018.8533248
- isbn
- 978-1-5386-7431-4
- url
- http://dblp.uni-trier.de/db/conf/sbcci/sbcci2018.html#NetoPMMRR18
Tags
Users
Comments and Reviewsshow / hide
Cite this publication
More citation styles
- please select -%0 Conference Paper
%1 conf/sbcci/NetoPMMRR18
%A Neto, Walter Lau
%A Possani, Vinicius N.
%A Marranghello, Felipe S.
%A Matos, Jody Maick
%A Reis, André Inácio
%A Ribas, Renato P.
%B SBCCI
%D 2018
%I IEEE
%K dblp
%P 1-6
%T Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.
%U http://dblp.uni-trier.de/db/conf/sbcci/sbcci2018.html#NetoPMMRR18
%@ 978-1-5386-7431-4
@inproceedings{conf/sbcci/NetoPMMRR18,
added-at = {2021-02-25T00:00:00.000+0100},
author = {Neto, Walter Lau and Possani, Vinicius N. and Marranghello, Felipe S. and Matos, Jody Maick and Reis, André Inácio and Ribas, Renato P.},
biburl = {https://www.bibsonomy.org/bibtex/2f088c6a78e6229f53a30e4ec933628b5/dblp},
booktitle = {SBCCI},
crossref = {conf/sbcci/2018},
ee = {https://doi.org/10.1109/SBCCI.2018.8533248},
interhash = {b6a4e65d6c5eca1e58ad7ad6056d226b},
intrahash = {f088c6a78e6229f53a30e4ec933628b5},
isbn = {978-1-5386-7431-4},
keywords = {dblp},
pages = {1-6},
publisher = {IEEE},
timestamp = {2024-04-10T06:33:06.000+0200},
title = {Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.},
url = {http://dblp.uni-trier.de/db/conf/sbcci/sbcci2018.html#NetoPMMRR18},
year = 2018
}