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Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.

, , , , , и . SBCCI, стр. 1-6. IEEE, (2018)

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André Reis

André Reis

Andre Reis

Inácio Barros

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A comparative study of CMOS gates with minimum transistor stacks., , , , и . SBCCI, стр. 93-98. ACM, (2007)Efficient method to compute minimum decision chains of Boolean functions., , , и . ACM Great Lakes Symposium on VLSI, стр. 419-422. ACM, (2011)Efficient Test Circuit to Qualify Logic Cells., , , и . ISCAS, стр. 2733-2736. IEEE, (2009)Read-polarity-once Boolean functions., , , и . SBCCI, стр. 1-6. IEEE, (2013)Tool integration using the web-services approach., , , и . ACM Great Lakes Symposium on VLSI, стр. 337-340. ACM, (2005)SOP based logic synthesis for memristive IMPLY stateful logic., , , и . ICCD, стр. 228-235. IEEE Computer Society, (2015)SIFU! - A Didactic Stuck-at Fault Simulator., , и . MSE, стр. 93-94. IEEE Computer Society, (2003)Fast disjoint transistor networks from BDDs., , , , , и . SBCCI, стр. 137-142. ACM, (2006)Modeling Subthreshold Leakage Current in General Transistor Networks., , , и . ISVLSI, стр. 512-513. IEEE Computer Society, (2007)Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering., , , , и . ISQED, стр. 47-52. IEEE Computer Society, (2008)