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Disambiguation of "Reis, André Inácio"

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Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.

, , , , , and . SBCCI, page 1-6. IEEE, (2018)

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André Reis

André Reis

Andre Reis

Inácio Barros

Isabel Inácio

 

Other publications of authors with the same name

A comparative study of CMOS gates with minimum transistor stacks., , , , and . SBCCI, page 93-98. ACM, (2007)Efficient method to compute minimum decision chains of Boolean functions., , , and . ACM Great Lakes Symposium on VLSI, page 419-422. ACM, (2011)Technology Mapping for Circuits with Simple Cells., , and . ISCAS, page 1-5. IEEE, (2018)Constructive AIG optimization considering input weights., , and . ISQED, page 769-776. IEEE, (2011)Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates., , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 474-484. Springer, (2007)Efficient Test Circuit to Qualify Logic Cells., , , and . ISCAS, page 2733-2736. IEEE, (2009)Lithography analysis of via-configurable transistor-array fabrics., , and . NORCHIP, page 1-4. IEEE, (2012)Analytical logical effort formulation for minimum active area under delay constraints., , , and . SBCCI, page 1-6. IEEE, (2013)Read-polarity-once Boolean functions., , , and . SBCCI, page 1-6. IEEE, (2013)Routing Resistance Influence in Loading Effect on Leakage Analysis., , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 317-325. Springer, (2009)