%0 Journal Article %1 journals/ejasp/SpiveyBN03 %A Spivey, Gary %A Bhattacharyya, Shuvra S. %A Nakajima, Kazuo %D 2003 %J EURASIP J. Adv. Signal Process. %K dblp %N 6 %P 565-579 %T Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems. %U http://dblp.uni-trier.de/db/journals/ejasp/ejasp2003.html#SpiveyBN03 %V 2003

@article{journals/ejasp/SpiveyBN03, added-at = {2020-03-12T00:00:00.000+0100}, author = {Spivey, Gary and Bhattacharyya, Shuvra S. and Nakajima, Kazuo}, biburl = {https://www.bibsonomy.org/bibtex/2c7acd5eaed67f23ba64f15db3c2d7f01/dblp}, ee = {https://doi.org/10.1155/S1110865703301039}, interhash = {bbdb0cd4094f02e9cc94ebcbb97bff07}, intrahash = {c7acd5eaed67f23ba64f15db3c2d7f01}, journal = {EURASIP J. Adv. Signal Process.}, keywords = {dblp}, number = 6, pages = {565-579}, timestamp = {2020-03-13T12:15:36.000+0100}, title = {Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems.}, url = {http://dblp.uni-trier.de/db/journals/ejasp/ejasp2003.html#SpiveyBN03}, volume = 2003, year = 2003 }