%0 Conference Paper %1 conf/aspdac/SuZHLRC22 %A Su, Shiyu %A Zhang, Qiaochu %A Hassanpourghadi, Mohsen %A Liu, Juzheng %A Rasul, Rezwan A. %A Chen, Mike Shuo-Wei %B ASP-DAC %D 2022 %I IEEE %K dblp %P 100-107 %T Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2022.html#SuZHLRC22 %@ 978-1-6654-2135-5

@inproceedings{conf/aspdac/SuZHLRC22, added-at = {2024-05-07T00:00:00.000+0200}, author = {Su, Shiyu and Zhang, Qiaochu and Hassanpourghadi, Mohsen and Liu, Juzheng and Rasul, Rezwan A. and Chen, Mike Shuo-Wei}, biburl = {https://www.bibsonomy.org/bibtex/24892caba2dec23bfc46545bb73418c89/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2022}, ee = {https://doi.org/10.1109/ASP-DAC52403.2022.9712577}, interhash = {bcc11587738ba679924a5d093edfec6c}, intrahash = {4892caba2dec23bfc46545bb73418c89}, isbn = {978-1-6654-2135-5}, keywords = {dblp}, pages = {100-107}, publisher = {IEEE}, timestamp = {2024-05-13T08:17:54.000+0200}, title = {Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2022.html#SuZHLRC22}, year = 2022 }