%0 Conference Paper %1 conf/vlsit/Chou0RLDSWBZ22 %A Chou, Teyuh %A Tang, Wei %A Rotaru, Mihai D. %A Liu, Chester %A Dutta, Rahul %A Siang, Sharon Lim Pei %A Wee, David Ho Soon %A Bhattacharya, Surya %A Zhang, Zhengya %B VLSI Technology and Circuits %D 2022 %I IEEE %K dblp %P 208-209 %T NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#Chou0RLDSWBZ22 %@ 978-1-6654-9772-5

@inproceedings{conf/vlsit/Chou0RLDSWBZ22, added-at = {2022-08-04T00:00:00.000+0200}, author = {Chou, Teyuh and Tang, Wei and Rotaru, Mihai D. and Liu, Chester and Dutta, Rahul and Siang, Sharon Lim Pei and Wee, David Ho Soon and Bhattacharya, Surya and Zhang, Zhengya}, biburl = {https://www.bibsonomy.org/bibtex/20a06bfabafb596a25812e4585f79d43d/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2022}, ee = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830249}, interhash = {bfd9815aefec854a3844fc0e297c5048}, intrahash = {0a06bfabafb596a25812e4585f79d43d}, isbn = {978-1-6654-9772-5}, keywords = {dblp}, pages = {208-209}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:06.000+0200}, title = {NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#Chou0RLDSWBZ22}, year = 2022 }