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Disambiguation of "Zhang, Zhengya"

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NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging.

, , , , , , , , and . VLSI Technology and Circuits, page 208-209. IEEE, (2022)

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Zhengya Yu

Zhang Zhang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)

Xianghong Zhang

Miao Zhang

 

Other publications of authors with the same name

Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes., , , , and . IEEE Trans. Inf. Theory, 56 (1): 181-201 (2010)NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging., , , , , , , , and . VLSI Technology and Circuits, page 208-209. IEEE, (2022)Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration., , , , , , , , , and 9 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)ANSA: Adaptive Near-Sensor Architecture for Dynamic DNN Processing in Compact Form Factors., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (3): 1256-1269 (March 2023)Point-X: A Spatial-Locality-Aware Architecture for Energy-Efficient Graph-Based Point-Cloud Deep Learning., and . MICRO, page 1078-1090. ACM, (2021)DNC-Aided SCL-Flip Decoding of Polar Codes., and . GLOBECOM, page 1-6. IEEE, (2021)1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks., , and . VLSIC, page 246-. IEEE, (2015)A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM., , , and . VLSIC, page 114-115. IEEE, (2012)Minimum supply voltage for sequential logic circuits in a 22nm technology., , , , and . ISLPED, page 181-186. IEEE, (2013)A 2.4-mm2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4×4 256-QAM MIMO in 65-nm CMOS., , and . IEEE J. Solid State Circuits, 54 (7): 2070-2080 (2019)