%0 Conference Paper %1 conf/vlsic/SatpathySKGGAKA19 %A Satpathy, Sudhir %A Suresh, Vikram B. %A Kumar, Raghavan %A Gopal, Vinodh %A Guilford, James %A Anders, Mark A. %A Kaul, Himanshu %A Agarwal, Amit %A Hsu, Steven %A Krishnamurthy, Ram %A De, Vivek %A Mathew, Sanu %B VLSI Circuits %D 2019 %I IEEE %K dblp %P 238- %T A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#SatpathySKGGAKA19 %@ 978-4-86348-720-8

@inproceedings{conf/vlsic/SatpathySKGGAKA19, added-at = {2022-02-25T00:00:00.000+0100}, author = {Satpathy, Sudhir and Suresh, Vikram B. and Kumar, Raghavan and Gopal, Vinodh and Guilford, James and Anders, Mark A. and Kaul, Himanshu and Agarwal, Amit and Hsu, Steven and Krishnamurthy, Ram and De, Vivek and Mathew, Sanu}, biburl = {https://www.bibsonomy.org/bibtex/24667bfaedb601bdd1817954da2f35815/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2019}, ee = {https://doi.org/10.23919/VLSIC.2019.8777934}, interhash = {c854adacbb3eca3e6f2a7b5728644414}, intrahash = {4667bfaedb601bdd1817954da2f35815}, isbn = {978-4-86348-720-8}, keywords = {dblp}, pages = {238-}, publisher = {IEEE}, timestamp = {2024-04-10T15:34:13.000+0200}, title = {A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#SatpathySKGGAKA19}, year = 2019 }