%0 Journal Article %1 journals/jssc/TakemotoHYY20 %A Takemoto, Takashi %A Hayashi, Masato %A Yoshimura, Chihiro %A Yamaoka, Masanao %D 2020 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 145-156 %T A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. %U http://dblp.uni-trier.de/db/journals/jssc/jssc55.html#TakemotoHYY20 %V 55

@article{journals/jssc/TakemotoHYY20, added-at = {2020-08-30T00:00:00.000+0200}, author = {Takemoto, Takashi and Hayashi, Masato and Yoshimura, Chihiro and Yamaoka, Masanao}, biburl = {https://www.bibsonomy.org/bibtex/201886ba0695918be9e0c528e058e137c/dblp}, ee = {https://doi.org/10.1109/JSSC.2019.2949230}, interhash = {ccb4264bfaeb1d46de6fbd3bc581a582}, intrahash = {01886ba0695918be9e0c528e058e137c}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {145-156}, timestamp = {2020-08-31T11:42:10.000+0200}, title = {A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc55.html#TakemotoHYY20}, volume = 55, year = 2020 }