%0 Conference Paper %1 conf/sc/ShivelyMCG89 %A Shively, Richard R. %A Morgan, E. B. %A Copley, T. W. %A Gorin, Allen L. %B SC %D 1989 %E Bailey, F. Ron %I ACM %K dblp %P 505-509 %T A high performance reconfigurable parallel processing architecture. %U http://dblp.uni-trier.de/db/conf/sc/sc1989.html#ShivelyMCG89 %@ 0-89791-341-8

@inproceedings{conf/sc/ShivelyMCG89, added-at = {2018-11-06T00:00:00.000+0100}, author = {Shively, Richard R. and Morgan, E. B. and Copley, T. W. and Gorin, Allen L.}, biburl = {https://www.bibsonomy.org/bibtex/2c4f40370d66d3c59f7d8479c08e200ae/dblp}, booktitle = {SC}, crossref = {conf/sc/1989}, editor = {Bailey, F. Ron}, ee = {https://doi.org/10.1145/76263.76319}, interhash = {d282c700f46afeb8f1a2ec9341b42b06}, intrahash = {c4f40370d66d3c59f7d8479c08e200ae}, isbn = {0-89791-341-8}, keywords = {dblp}, pages = {505-509}, publisher = {ACM}, timestamp = {2018-11-07T12:45:04.000+0100}, title = {A high performance reconfigurable parallel processing architecture.}, url = {http://dblp.uni-trier.de/db/conf/sc/sc1989.html#ShivelyMCG89}, year = 1989 }