%0 Conference Paper %1 conf/mse/ClarkVHDW17 %A Clark, Lawrence T. %A Vashishtha, Vinay %A Harris, David M. %A Dietrich, Samuel %A Wang, Zunyan %B MSE %D 2017 %I IEEE %K dblp %P 1-4 %T Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit. %U http://dblp.uni-trier.de/db/conf/mse/mse2017.html#ClarkVHDW17 %@ 978-1-5090-6431-1

@inproceedings{conf/mse/ClarkVHDW17, added-at = {2017-06-16T00:00:00.000+0200}, author = {Clark, Lawrence T. and Vashishtha, Vinay and Harris, David M. and Dietrich, Samuel and Wang, Zunyan}, biburl = {https://www.bibsonomy.org/bibtex/2d4894179ab87d952d22ff1d37e49ff5b/dblp}, booktitle = {MSE}, crossref = {conf/mse/2017}, ee = {https://doi.org/10.1109/MSE.2017.7945071}, interhash = {e0f1142d338543589b09074c996d94db}, intrahash = {d4894179ab87d952d22ff1d37e49ff5b}, isbn = {978-1-5090-6431-1}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2019-10-17T20:53:32.000+0200}, title = {Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit.}, url = {http://dblp.uni-trier.de/db/conf/mse/mse2017.html#ClarkVHDW17}, year = 2017 }