%0 Conference Paper %1 conf/aspdac/NiitsuHHOSKYK13 %A Niitsu, Kiichi %A Harigai, Naohiro %A Hirabayashi, Daiki %A Oki, Daiki %A Sakurai, Masato %A Kobayashi, Osamu %A Yamaguchi, Takahiro J. %A Kobayashi, Haruo %B ASP-DAC %D 2013 %I IEEE %K dblp %P 103-104 %T Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#NiitsuHHOSKYK13 %@ 978-1-4673-3029-9

@inproceedings{conf/aspdac/NiitsuHHOSKYK13, added-at = {2023-03-21T00:00:00.000+0100}, author = {Niitsu, Kiichi and Harigai, Naohiro and Hirabayashi, Daiki and Oki, Daiki and Sakurai, Masato and Kobayashi, Osamu and Yamaguchi, Takahiro J. and Kobayashi, Haruo}, biburl = {https://www.bibsonomy.org/bibtex/2374cb4ae70420a5f06a86caec29a1a83/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2013}, ee = {https://doi.org/10.1109/ASPDAC.2013.6509577}, interhash = {e5eae801844dfc0df2acfa4d687e842f}, intrahash = {374cb4ae70420a5f06a86caec29a1a83}, isbn = {978-1-4673-3029-9}, keywords = {dblp}, pages = {103-104}, publisher = {IEEE}, timestamp = {2024-04-10T04:16:21.000+0200}, title = {Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#NiitsuHHOSKYK13}, year = 2013 }