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Disambiguation of "Kobayashi, Osamu"

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Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

, , , , , , , and . ASP-DAC, page 103-104. IEEE, (2013)

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Osamu Ohguchi

Osamu Omuro

Osamu Terakado

Osamu Yamada

Osamu Watanabe

 

Other publications of authors with the same name

Multi-bit sigma-delta TDC architecture with self-calibration., , , , , , , , , and 3 other author(s). APCCAS, page 671-674. IEEE, (2012)Two-Tone Signal Generation for Communication Application ADC Testing., , , , , , , and . Asian Test Symposium, page 179-184. IEEE Computer Society, (2012)Two-Tone Signal Generation for ADC Testing., , , , , , , and . IEICE Trans. Electron., 96-C (6): 850-858 (2013)30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology., , , , , , , , , and 49 other author(s). ISSCC, page 428-430. IEEE, (2021)Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . ASP-DAC, page 103-104. IEEE, (2013)What Should Software Practitioners Know for Adopting Product Line Software Engineering?.. APSEC, page 565-566. IEEE Computer Society, (2004)A clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . VLSIC, page 142-143. IEEE, (2012)A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs., , , , , and . ESSCIRC, page 69-72. IEEE, (2012)Analysis of the interaction between practices for introducing XP effectively., , , and . ICSE, page 544-550. ACM, (2006)Low-distortion signal generation for ADC testing., , , , , and . ITC, page 1-10. IEEE Computer Society, (2014)