%0 Conference Paper %1 conf/micro/JingWFYJLL16 %A Jing, Naifeng %A Wang, Jianfei %A Fan, Fengfeng %A Yu, Wenkang %A Jiang, Li %A Li, Chao %A Liang, Xiaoyao %B MICRO %D 2016 %I IEEE Computer Society %K dblp %P 14:1-14:12 %T Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs. %U http://dblp.uni-trier.de/db/conf/micro/micro2016.html#JingWFYJLL16 %@ 978-1-5090-3508-3

@inproceedings{conf/micro/JingWFYJLL16, added-at = {2022-05-31T00:00:00.000+0200}, author = {Jing, Naifeng and Wang, Jianfei and Fan, Fengfeng and Yu, Wenkang and Jiang, Li and Li, Chao and Liang, Xiaoyao}, biburl = {https://www.bibsonomy.org/bibtex/2e4e3d9ac46da64408e10b4487111fbc6/dblp}, booktitle = {MICRO}, crossref = {conf/micro/2016}, ee = {http://dl.acm.org/citation.cfm?id=3195655}, interhash = {ea2fbe239a992fbb46f02b8079b34fd0}, intrahash = {e4e3d9ac46da64408e10b4487111fbc6}, isbn = {978-1-5090-3508-3}, keywords = {dblp}, pages = {14:1-14:12}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T20:38:11.000+0200}, title = {Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.}, url = {http://dblp.uni-trier.de/db/conf/micro/micro2016.html#JingWFYJLL16}, year = 2016 }