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Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.

N. Jing, J. Wang, F. Fan, W. Yu, L. Jiang, C. Li, and X. Liang. MICRO, page 14:1-14:12. IEEE Computer Society, (2016)

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Liang Liang

Liang-Liang Fu

Qian Liang

Tzan Jing Liang

Shu Chuan Liang

Other publications of authors with the same name

A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs.T. Li, F. Xie, X. Liang, Q. Xu, K. Chakrabarty, N. Jing, and L. Jiang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (7): 1192-1205 (2016)Mitigating the Impact of Process Variations on Processor Register Files and Execution Units.X. Liang, and D. Brooks. MICRO, page 504-514. IEEE Computer Society, (2006)Process Variation Tolerant 3T1D-Based Cache Architectures.X. Liang, R. Canal, G. Wei, and D. Brooks. MICRO, page 15-26. IEEE Computer Society, (2007)N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores.Y. Gong, Z. Xu, Z. He, W. Zhang, X. Tu, X. Liang, and L. Jiang. FPGA, page 112-122. ACM, (2022)PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation.Z. Song, N. Jing, and X. Liang. ACM TUR-C, page 49-50. ACM, (2023)AXNet: approximate computing using an end-to-end trainable neural network.Z. Peng, X. Chen, C. Xu, N. Jing, X. Liang, C. Lu, and L. Jiang. ICCAD, page 11:1-11:8. ACM, (2018)AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity.X. Lin, G. Li, Z. Liu, Y. Liu, F. Zhang, Z. Song, N. Jing, and X. Liang. DAC, page 1-6. IEEE, (2023)HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing.H. Ji, L. Jiang, T. Li, N. Jing, J. Ke, and X. Liang. ASP-DAC, page 249-254. ACM, (2019)Approximate Random Dropout for DNN training acceleration in GPGPU.Z. Song, R. Wang, D. Ru, Z. Peng, H. Huang, H. Zhao, X. Liang, and L. Jiang. DATE, page 108-113. IEEE, (2019)Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar.L. Chen, J. Li, Y. Chen, Q. Deng, J. Shen, X. Liang, and L. Jiang. DATE, page 19-24. IEEE, (2017)

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Disambiguation of "Liang, Xiaoyao"

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Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.

Please choose a person to relate this publication to

Liang Liang

Liang-Liang Fu

Qian Liang

Tzan Jing Liang

Shu Chuan Liang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Liang, Xiaoyao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.

Please choose a person to relate this publication to

Liang Liang

Liang-Liang Fu

Qian Liang

Tzan Jing Liang

Shu Chuan Liang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.