Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.
S. Gao, K. Seto, S. Komatsu, and M. Fujita. IESS, volume 231 of IFIP Advances in Information and Communication Technology, page 121-134. Springer, (2007)
@inproceedings{conf/iess/GaoSKF07,
added-at = {2018-06-26T00:00:00.000+0200},
author = {Gao, Shanghua and Seto, Kenshu and Komatsu, Satoshi and Fujita, Masahiro},
biburl = {https://www.bibsonomy.org/bibtex/27e00d8d67ef14278514f84438889b32a/dblp},
booktitle = {IESS},
crossref = {conf/iess/2007},
editor = {Rettberg, Achim and Zanella, Mauro Cesar and Dömer, Rainer and Gerstlauer, Andreas and Rammig, Franz-Josef},
ee = {https://doi.org/10.1007/978-0-387-72258-0_11},
interhash = {f3d56734ed349637c8117d673d3b0046},
intrahash = {7e00d8d67ef14278514f84438889b32a},
isbn = {978-0-387-72257-3},
keywords = {dblp},
pages = {121-134},
publisher = {Springer},
series = {IFIP Advances in Information and Communication Technology},
timestamp = {2018-06-27T12:27:52.000+0200},
title = {Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.},
url = {http://dblp.uni-trier.de/db/conf/iess/iess2007.html#GaoSKF07},
volume = 231,
year = 2007
}