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Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.

, , , and . IESS, volume 231 of IFIP Advances in Information and Communication Technology, page 121-134. Springer, (2007)

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Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays., , , and . FPT, page 137-144. IEEE, (2005)Engineering Changes in Field Modifiable Architectures., , , , and . MEMOCODE, page 87-94. IEEE Computer Society, (2003)Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis., , , , and . IWLS, page 103-108. (2002)Scalar replacement in the presence of multiple write accesses for high-level synthesis.. DATE, page 26-31. IEEE, (2021)Custom Instruction Generation with High-Level Synthesis., and . SASP, page 14-19. IEEE Computer Society, (2008)Small Memory Footprint Neural Network Accelerators., , , , and . ISQED, page 253-258. IEEE, (2019)Dynamically reconfigurable protocol transducer., , , , and . FPT, page 341-344. IEEE, (2006)Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures., , , and . IESS, volume 231 of IFIP Advances in Information and Communication Technology, page 121-134. Springer, (2007)SAT-based resource binding for reducing critical path delays., , , and . FPL, page 507-510. IEEE, (2008)Loop Fusion with Outer Loop Shifting for High-level Synthesis., and . IPSJ Trans. Syst. LSI Des. Methodol., (2013)